1. Field of the Invention
The present invention relates to a method for forming, by sequential tridimensional integration, a level of an integrated circuit on an existing level.
2. Discussion of the Related Art
Currently, in the field of integrated circuits, one of the known solutions to form increasingly compact systems is to perform a three-dimensional integration. Such an integration comprises forming several semiconductor substrates, on and inside of which are formed electronic components, above one another, and connecting components of different levels together, for example through substrates. This type of integration enables increasing the integration density and the number of integrated functionalities. This type of integration also reduces the length of interconnects between the different integrated circuit elements and decreases the power consumption.
So-called sequential integration methods are known, in which the tridimensional architecture is created one level after the other, in a vertical sequence. Components are formed inside and on top of a first substrate, after which a second substrate is either fixed above the first substrate, or formed by recrystallization of amorphous silicon or polysilicon. In this last case, it is difficult to obtain a strict single-crystal silicon substrate. Components are then formed inside and on top of the second substrate, and so on.
FIGS. 1A to 1F illustrate steps of a method for forming a level of a tridimensional integrated circuit by sequential integration. This method is especially described in the publication entitled “65 nm High Performance SRAM Technology with 25 F2, 0.16 μm2 S3 (Stacked Single-crystal Si) SRAM Cell, and Stacked Peripheral SSTFT for Ultra High Density and High Speed Applications”, by H. Lim et al., Proceedings of ESSDERC, 2005.
FIG. 1A illustrates a level of a tridimensional integrated circuit and FIG. 1B illustrates a structure based on which an upper level of the integrated circuit is formed, by sequential integration.
FIG. 1A shows a substrate 10 on top and inside of which electronic components are formed. In the shown examples, gates of transistors 12 are formed at the surface of substrate 10. Of course, other electronic components may be formed inside and on top of substrate 10. A dielectric material stack 14 in which interconnection elements (conductive tracks and vias) may be provided is formed on components 12. In the following description, stacks such as stack 14 will be called “interconnect stack”, although the metal tracks and vias in such stacks are optional.
FIG. 1B shows a structure comprising a single-crystal silicon substrate 16 formed on an insulating layer 18, itself extending over a support 20, for example, a semiconductor support. The structure of FIG. 1B may be formed by any so-called SOI (silicon on insulator) method.
At the step illustrated in FIG. 1C, the free surface of silicon substrate 16 has been bonded, in any known fashion, for example, by molecular bonding, at the surface of interconnect stack 14 of the structure shown in FIG. 1A.
At the step illustrated in FIG. 1D, semiconductor support 20 and insulating layer 18 have been eliminated. A structure in which a second silicon substrate 16 extends on interconnect stack 14 is thus obtained.
At the step illustrated in FIG. 1E, electronic components, for example, insulated-gate transistors 22, are formed inside and on top of silicon substrate 16.
At the step illustrated in FIG. 1F, a second interconnect stack 24 is formed on electronic components 22. Stack 24 may comprise interconnection elements (conductive tracks and vias) and may be electrically connected to a metallization of stack 14 or directly connected to transistors 12 if no interconnection element is formed in stack 14. A structure is thus obtained, above which other substrates, and thus other levels of the tridimensional integrated circuit may be formed, by following the same procedure as for the forming of silicon substrate 16.
In this method, the components formed on top and inside of substrate 16 are formed during steps independent from the forming of substrate 16. Especially, the forming of a silicon oxide gate insulator for transistors 22 needs various types of chemical vapor depositions (for example, PECVD, for Plasma-Enhanced Chemical Vapor Deposition, HDP-CVD, for High-Density Plasma Chemical Vapor Deposition, ALD, for Atomic Layer Deposition, or again SACVD, for Sub-Atmospheric Chemical Vapor Deposition). Such methods generally do not enable to obtain layers having a thickness defined with an accuracy better than 5 nm. Further, for all these processes, a major disadvantage is the forming of an oxide exhibiting a medium-grade silicon interface, at least of lower grade than so-called “thermal” oxides formed by thermal oxidation of the silicon surface. This is due to the presence of traps in the oxide formed by deposition and of dangling bonds at the interface between the silicon and the oxide, which is not the case for oxide layers obtained by oxidation (thermal oxide).
Methods for forming thermal oxide layers require silicon heating steps at high temperature, generally on the order of 1000° C., which makes such methods incompatible with tridimensional device forming methods, electronic components being present in lower levels of the device. Indeed, too high temperatures destroy the characteristics of components such as transistors. Temperatures compatible with such components, typically lower than 700° C., do not provide sufficient oxidation kinetics.
Thus, there is a need for a method for manufacturing a tridimensional integrated circuit by sequential integration in which, in upper circuit levels, the gate oxides are of high grade.